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FEATURES 5 V Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24 Bits, 192 kHz Sample Rate Accepts a Wide Range of Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz Multibit Sigma-Delta Modulator with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC--Least Sensitive to Jitter Single-Ended Output for Easy Use 108 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) 109 dB Dynamic Range (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) -96 dB THD + N (Stereo) 75 dB Stop Band Attenuation On-Chip Clickless Volume Control Hardware and Software Controllable Clickless Mute Serial (SPI) Control for: Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-Emphasis Digital De-Emphasis Processing for 32 kHz, 44.1 kHz, and 48 kHz Sample Rates Programmable Dual Fractional-N PLL Clock Generator 27 MHz Master Clock Oscillator Better than 100 ps rms Master Clock Jitter Generated System Clocks SCLK0: 33.8688 MHz SCLK1: 22.5792 MHz, 24.576 MHz, 33.8688 MHz, or 36.864 MHz SCLK2: 16.9344 MHz
PLL/Multibit - DAC AD1958
Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible, and DSP Serial Port Modes 28-Lead SSOP Plastic Package APPLICATIONS DVD, CD, Home Theater Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors PRODUCT OVERVIEW
The AD1958 is a complete high-performance single-chip stereo digital audio playback system. It is comprised of a multibit sigmadelta modulator, digital interpolation filters, and analog output drive circuitry with an on-board dual PLL clock generator. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The AD1958 is fully compatible with all known DVD formats including 96 kHz and 192 kHz sample frequencies and 24 bits. It also is backwards-compatible by supporting 50 s/15 s digital de-emphasis for "redbook" compact discs, as well as de-emphasis at 32 kHz and 48 kHz sample rates. The AD1958 has a simple but flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers, and sample rate converters. The AD1958 can be configured in left-justified, I2S, right-justified, or DSP serial-port-compatible modes. It can support 16, 20, and 24 bits in all modes. The AD1958 accepts serial audio data in MSB first, two's-complement format, and operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and housed in a 28-lead SSOP package for operation over the temperature range -40C to +105C.
FUNCTIONAL BLOCK DIAGRAM
XIN XOUT MCLK LOOP FILTERS 2 CLOCK OUTPUTS 3 CONTROL DATA INPUT 3
AD1958
OSC
PLL CIRCUIT
SERIAL CONTROL INTERFACE
VOLTAGE REFERENCE
ATTEN/MUTE 16-/20-/24BIT DIGITAL DATA INPUT SERIAL DATA INTERFACE ATTEN/MUTE
8 fS INTERPOLATOR
MULTIBIT SIGMA-DELTA MODULATOR
DAC
OUTPUT BUFFER
L ANALOG OUTPUTS
3
8 fS INTERPOLATOR
MULTIBIT SIGMA-DELTA MODULATOR
DAC
OUTPUT BUFFER
R
2 RESET MUTE ZERO FLAG PLL SUPPLY
2 DIGITAL SUPPLY
3 ANALOG SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD1958-SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD, PVDD) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO
ANALOG PERFORMANCE
5.0 V 25C 12.288 MHz (256 x fS Mode) 996.0938 Hz, 0 dB Full Scale 48 kHz 20 Hz to 20 kHz 24 Bits 100 pF 47 k 2.0 V 0.8 V Min Typ 24 105 108 102 -90 105 109 -96 27 33.8688 12.288 22.5792 110 60 50 50 3.17 2 -90 2.39 -5 -0.15 -25 2.0 0.015 150 -3 -120 0.1 -100 +5 +0.15 250 +20 Max Unit Bits dB dB dB dB dB MHz MHz MHz MHz ps rms ps rms % % V p-p pF dB V % dB ppm/C mV dB Degrees dB dB
Resolution Signal-to-Noise Ratio (20 Hz to 20 kHz) No Filter (Stereo) With A-Weighted Filter (Stereo) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter (Stereo) With A-Weighted Filter (Stereo) Total Harmonic Distortion + Noise (Stereo) PLL Performance Master Clock Input Frequency Generated System Clocks SCLK0 SCLK1 SCLK2 Jitter (SCLK0 and SCLK1) Jitter (MCLK) Duty Cycle (SCLK0, SCLK1)1 Duty Cycle (MCLK) Analog Outputs Single-Ended Output Range ( Full Scale) Output Capacitance at Each Output Pin Out-of-Band Energy (0.5 x fS to 100 kHz) VREF (FILTR) DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift DC Offset Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Mute Attenuation De-Emphasis Gain Error
175 100 51
49
0.1
NOTES 1 In some combinations with Clock Configuration Mode = 1 (see Table III), SCLK will not be 50%. 2 Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice.
DIGITAL I/O (-40C to +105C )
Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Input Capacitance
Specifications subject to change without notice.
Typ
Max 0.8 10 10
Unit V V A A V V pF REV. 0
2.0
3.5 0.4 20 -2-
AD1958
TEMPERATURE RANGE
Min Specifications Guaranteed Functionality Guaranteed Storage -40 -55
Typ 25
Max +105* +125
Unit C C C
NOTE *105C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85 C for 2-layer board, 2 oz. layers. Specifications subject to change without notice.
POWER
Min Supplies Voltage, Analog Digital PLL Analog Current Digital Current PLL Current Dissipation Operation--All Supplies Operation--Analog Supply Operation--Digital Supply Operation--PLL Supply Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice.
Typ 5 36 25 30 455 180 125 150 -60 -50
Max 5.50 41 29 34 540
Unit V mA mA mA mW mW mW mW dB dB
4.50
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz) 44.1 48 96 192
Pass Band (kHz) DC-20 DC-21.8 DC-39.95 DC-87.2
Stop Band (kHz) 24.1-328.7 26.23-358.28 56.9-327.65 117-327.65
Stop Band Attenuation (dB) 75 75 75 60
Pass Band Ripple (dB) 0.0002 0.0002 0.0005 0/-0.04 (DC-21.8 kHz) 0/-0.5 (DC-65.4 kHz) 0/-1.5 (DC-87.2 kHz)
Specifications subject to change without notice.
GROUP DELAY
Chip Mode INT8x Mode INT4x Mode INT2x Mode
Group Delay Calculation 24.625/fS 15.75/fS 14/fS
fS 48 kHz 96 kHz 192 kHz
Group Delay 513 164 72.91
Unit s s s
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over -40C to +105 C, AVDD = DVDD = PVDD = 5.0 V
10%)
Min tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tRSTL REV. 0 MCLK Period (FMCLK = 256 x FLRCLK) MCLK LO Pulsewidth (All Modes) MCLK HI Pulsewidth (All Modes) BCLK HI Pulsewidth BCLK LO Pulsewidth BCLK Period LRCLK Setup LRCLK Hold (DSP Serial Port Mode Only) SDATA Setup SDATA Hold RST LO Pulsewidth -3- 54 15 10 20 20 60 20 20 15 15 15
Unit ns ns ns ns ns ns ns ns ns ns ns
Specifications subject to change without notice.
AD1958
ABSOLUTE MAXIMUM RATINGS* PACKAGE CHARACTERISTICS
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V Digital Inputs . . . . . . . . . . DGND - 0.3 V to DVDD + 0.3 V Analog Inputs . . . . . . . . . . AGND - 0.3 V to AVDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to + 0.3 V Reference Voltage . . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2 Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Min (Thermal Resistance) Junction-to-Ambient (2-Layer Board) JA (Thermal Resistance) Junction-to-Ambient (4-Layer Board-- 2 Signal, 2 Planes) JA (Thermal Resistance) Junction-to-Case
JA
Typ 109.0
Max
Unit C/W C/W
78.58
39.0
C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1958 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD1958YRS AD1958YRSRL EVAL-AD1958EB
Temperature -40C to +105 C -40C to +105 C
Package Description 28-Lead Small Outline Package 28-Lead Small Outline Package Evaluation Board
PIN CONFIGURATION
Package Option RS-28 RS-28 on 13" Reels
CCLK 1 CLATCH 2 RESET 3 LRCLK 4 BCLK 5 SDATA 6 DVDD 7
28 27 26 25 24
CDATA MUTE ZERO FILTB AVDD OUTL
AD1958
23
TOP VIEW 22 AGND1 DGND 8 (Not to Scale) 21 FLTR SCLK0 9 SCLK1 10 SCLK2 11 MCLK 12 XOUT 13 XIN 14
20 19 18 17 16 15
OUTR AGND0 LF1 LF0 PGND PVDD
-4-
REV. 0
AD1958
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3
Input/Output I I I
Mnemonic CCLK CLATCH RESET
Description Control Clock Input for Control Data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Latch Input for Control Data Reset. The AD1958 is placed in a reset mode when this pin is held LO. The serial control port registers are reset to their default values. Set HI for normal operation. Left/Right Clock Input for Input Data. Must run continuously. Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a burst fashion. Serial input, MSB first, containing two channels of 16/20/24 bits of two'scomplement data per channel. Digital Power Supply Connect to Digital 5 V Supply Digital Ground 33.8688 MHz Clock Output 256/384/512/768 fS Output 16.9344 MHz/22.5792 MHz/512 fS Output 27 MHz Master Clock Output/256 fS DAC Clock Input 27 MHz Crystal Oscillator Output 27 MHz Crystal Oscillator/External Clock Input PLL Power Supply. Connect to PLL 5 V Supply. PLL Ground PLL0 Loop Filter PLL1 Loop Filter Analog Ground Right Channel Positive Line Level Analog Output Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 F and 0.1 F capacitors to AGND. Analog Ground Left Channel Line Level Analog Output Analog Power Supply. Connect to Analog 5 V Supply. Filter Capacitor Connection. Connect 10 F Capacitor to AGND. Zero Flag Output. This pin goes HI when both channels have zero signal input for more than 1024 L/R Clock Cycles. Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for normal operation. Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used for specifying channel-specific attenuation and mute. into the audio band; care should be exercised in selecting these components. The FILTB and FILTR pins should be bypassed by external capacitors to ground. The FILTB pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR (VREF ~ 2.39 V) can be used to bias external op amps used to filter the output signals. The DAC master clock frequency is 256 fS for the 32 kHz-48 kHz range (8 interpolation, see Table I). For the 96 kHz range (4 interpolation) this is 128 fS. At 192 kHz (2 interpolation), this is 64 fS. It is supplied internally from the PLL clock system when MCLK mode is set to Output in the PLL Control Register. When the MCLK mode is changed to Input, it must be supplied from an external source connected to MCLK. The output from the 27 MHz PLL clock is disabled in this case. -5-
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
I I I I I O O O I/O O I
LRCLK BCLK SDATA DVDD DGND SCLK0 SCLK1 SCLK2 MCLK XOUT XIN PVDD PGND LF0 LF1 AGND0 OUTR FILTR AGND1 OUTL AVDD FILTB ZERO MUTE CDATA
O O I O
O I I
FUNCTIONAL DESCRIPTION DAC
The AD1958 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 16384 linear steps. Digital inputs are supplied through a serial data input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK. Each analog output pin sits at a dc level of VREF (present at FILTR), and swings 1.585 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high-frequency noise present on the output pins. The output phase can be changed in an SPI control register to accommodate inverting and noninverting filters. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down REV. 0
AD1958
Table I. DAC Control Register Bit 11:10 Interpolation Factor 00 = 8x* 01 = 4x 10 = 2x 11 = Not Allowed
*Default Setting
Bit 9:8 Serial Data Width 00 = 24 Bits* 01 = 20 Bits 10 = 16 Bits 11 = 16 Bits
Bit 7 Output Phase 0 = Noninverted* 1 = Inverted
Bit 6 Soft Mute 0 = No Mute* 1 = Muted
Bit 5:4 Serial Data Format 00 = I2S* 00 = Right Justified 10 = DSP 11 = Left Justified
Bit 3:2 De-Emphasis Filter 00 = None* 01 = 44.1 kHz 10 = 32 kHz 11 = 48 kHz
Bit 1:0 SPI Register Address 01
PLL CLOCK SYSTEM
Table II. DAC Volume Registers Bit 15:2 Volume 14 Bits, Unsigned 14 Bits, Unsigned
Default is full volume
The PLL clock system is expected to be run from a 27 MHz master clock supplied by the on-board crystal oscillator or an external source connected to XIN. With the MCLK mode set to Output, the 27 MHz clock is buffered out to the MCLK pin. When set to Input, this pin is the 256 fS master clock input for the DAC. SCLK0 is always set to 33.8688 MHz. SCLK1 is intended to be used as a master audio clock and will be a multiple of the sample rate set in the PLL control register (see Table III). In Mode 0 (Bit 8), it can be set to 512 or 768 times either 44.1 kHz or 48 kHz. SCLK2 will be 16.3944 MHz (384 44.1 kHz). In Mode 1, SCLK1 can be set to 256, 384, 512, or 768 times 32 kHz, 44.1 kHz, or 48 kHz. SCLK2 can be set to a constant 22.5792 MHz (512 44.1 kHz) or 512 fS. There are two loop filter pins, LF0 and LF1. They should each be bypassed to PVDD by a network consisting of a 33 nF capacitor in series with a 750 resistor, paralleled with a 1.8 nF capacitor. The 27 MHz Master Clock oscillator should have a crystal cut for an 18 pF load connected between XIN and XOUT, with 22 pF capacitors connected from XIN and XOUT to PGND.
Bit 1:0 SPI Register Address 00 = Left Volume 10 = Right Volume
RESET/POWER-DOWN
RESET will set the control registers to their default settings. The chip should be reset on power-up. After reset is deasserted, the part will come out of reset on the next rising LRCLK.
SERIAL CONTROL PORT
The AD1958 has an SPI-compatible control port to permit programming the internal control registers for the PLL and DAC. The DAC output levels may be independently programmed by means of an internal digital attenuator adjustable in 16384 linear steps.
Table III. PLL Control Register Bit 11 PLL2 PowerDown 0 = On1 1 = PD Bit 10 PLL1 PowerDown 0 = On1 1 = PD Bit 9 XTAL PowerDown 0 = On1 1 = PD Bit 8 Clock Configuration 0 = Mode 01 Bit 7:6 Bit 5 SCLK1 Select Bit 4 Frequency Double2 Reserved Set to 0 Bit 3 SCLK2 Select Reserved Set to 0 Bit 2 MCLK Mode Bit 1:0 SPI Register Address
fS
SCLK1 = 000: 36.864 MHz1 100: 24.576 MHz 110: 33.8688 MHz 111: 22.5792 MHz Other combinations reserved SCLK2 = 16.9344 MHz 00 = 48 kHz 01 = Not Allowed 10 = 32 kHz 11 = 44.1 kHz 0 = 256 fS 1 = 384 fS
0 = Output1 11 1 = Input
1 = Mode 1
0 = Normal 0 = 22.5792 MHz 1= 1 = 512 fS2 fNOMINAL 2
NOTES 1 Default Setting 2 In Mode 1, Frequency Double affects SCLK1 always and SCLK2 in 512
fS mode.
-6-
REV. 0
AD1958
The SPI control port is a 3-wire serial control port. The format is similar to the Motorola SPI format except the input data word is 16 bits wide. Max serial bit clock frequency is 8 MHz and may be completely asynchronous to the PLL system or the DAC. Figure 1 shows the format of the SPI signal. Note that the CCLK can be gated or continuous, CLATCH should be low during the 16 active clocks.
POWER SUPPLY AND VOLTAGE REFERENCE
is expected that the digital and PLL sections will be run from a common supply but isolated from one another. It is important that the analog supply be as clean as possible. The internal voltage reference is brought out on Pin 21 (FILTR) and should be bypassed as close as possible to the chip with a parallel combination of 10 F and 100 nF. The reference voltage may be used to bias external op amps to the common-mode voltage of the analog output signal pins. The current drawn from the FILTR pin should be limited to less than 50 A.
SERIAL DATA PORTS--DATA FORMAT
The AD1958 is designed for five-volt supplies. Separate power supply pins are provided for the analog, digital, and PLL sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise. A bulk aluminum electrolytic capacitor of at least 22 F should also be provided on the same PC board. For best performance it is recommended that the analog supply be separate from the digital and PLL supply. It is recommended that all supplies be isolated by ferrite beads in series with each supply. It
The DAC serial data input mode defaults to I2S. By changing Bits 4 and 5 in the DAC control register, the mode can be changed to RJ, DSP, or LJ. The word width defaults to 24 bits but can be changed by programming Bits 8 and 9 in the DAC Control Register. Figure 2 shows the serial mode formats.
CLATCH CCLK CDATA D15 D14 D0
Figure 1. Format of SPI Signal
LRCLK BCLK SDATA MSB LSB MSB LSB RIGHT CHANNEL
LEFT CHANNEL
LEFT-JUSTIFIED MODE--16 TO 24 BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB LEFT CHANNEL RIGHT CHANNEL
12S MODE--16 TO 24 BITS PER CHANNEL LRCLK LEFT CHANNEL BCLK SDATA MSB LSB MSB LSB RIGHT CHANNEL
RIGHT-JUSTIFIED MODE--SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB
DSP MODE--16 TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 fS. 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 2. Stereo Serial Modes
REV. 0
-7-
AD1958
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Small Outline Package (SSOP) (RS-28)
C02708-0-10/01(0)
8 0 0.03 (0.762) 0.022 (0.558) 0.407 (10.34) 0.397 (10.08)
28
15
0.212 (5.38) 0.205 (5.21) PIN 1
1 14
0.311 (7.9) 0.301 (7.64)
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) SEATING 0.010 (0.25) PLANE
0.009 (0.229) 0.005 (0.127)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-8-
REV. 0
PRINTED IN U.S.A.

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